In the manufacture of semiconductor wafers and integrated circuits, metal films are deposited on semiconductor substrates, oxides and other dielectrics. These metal films are used for different purposes, such as forming interconnect lines, metallic contacts, conductive vias, metallic interconnects and other conductive features on and above various surfaces of semiconductor wafers.
Typically, aluminum has been a preferred conductive metal because it avoids various problems, such as a high contact resistance with silicon, which normally accompanies the use of gold and copper. Copper also suffers drawbacks compared to aluminum because copper migrates into device areas, causing problems in device performance. Aluminum, on the other hand, has good adhesion to silicon dioxide and performs well with plasma etching, as compared to copper, which does not perform adequately with plasma etching processes.
Recently, greater interest has been shown by manufacturers of semiconductor devices in the use of copper and copper alloys for metallization patterns, such as in conductive vias and patterns. Copper has a lower resistivity than aluminum. Unfortunately, the standard processes used for pattern definition with semiconductors have not been adequately used with copper integrated circuit metallization. These processes include conventional dry etched techniques and selective deposition techniques. However, chemical mechanical polishing (CMP) techniques have been found useful in patterning copper layers. A drawback with CMP is that copper layers and vias are prone to heavy oxidation, which can cause dishing during the chemical mechanical polishing step. In one prior art technique, an HF wet cleaning step has been added to copper. This could include in one of the processing steps an anode water treatment. This can occur before HF clean and after CMP. However, this prior art technique is inefficient.